A video signal delivered from a personal computer or EWS (engineering work station) is changed in signal level in a specific period (hereinafter called "dot period") shorter than a horizontal synchronizing signal, and in the case of display in liquid crystal such as matrix display device, or in the case of signal processing by writing into a memory, a clock coinciding with the dot period (hereinafter called dot clock) is needed as a synchronizing signal.
Few personal computers, however, deliver dot clock, and therefore when displaying a video signal delivered from a personal computer, the image display device has a dot clock reproducing apparatus for reproducing the dot clock by multiplying the horizontal synchronizing signal.
For the conventional dot clock reproducing apparatus, however, various adjustments are indispensable, owing to the necessity of reproducing dot clock frequency of varied video signal sources from numerous personal computers, and the necessity of completely reproducing and restoring phase deviation between horizontal synchronizing signal and video signal due to the difference in the transmission route even in same video signal source. More specifically, the user must adjust manually by connecting a video signal source to the image display device, displaying the image of finer vertical lines than in the personal computer, and adjusting the multiplying factor of the PLL circuit of the dot clock reproducing apparatus, so that the vertical lines may be observed clearly.
This adjustment was disclosed as an example of automatic reproduction of a dot clock in Japanese Laid-open Patent 5-66752.
FIG. 26 shows a constitution of a conventional dot clock reproducing apparatus, in which reference 21 is an edge detector of video signal changing in dot period, 22 is a period measuring unit for measuring the period by counting high frequency pulses generated by a pulse oscillator 23 between an output edge of the edge detector and an edge of horizontal synchronizing signal, 23 is a pulse generator for generating a high frequency pulse used in period measurement in the period measuring unit, and 24 is an operation unit for setting the frequency of sampling clock to be created in a PLL circuit 25 by calculating the output of the period measuring unit.
In this constitution, however, in the case of XGA (Extended Graphic Array), since the dot clock frequency is very high, from 60 MHz to 80 MHz, the output in the pulse generator oscillated for measurement of period is required to be a still higher frequency, and the circuit for composing the period measuring unit requires parts of high performance corresponding to the very high frequency, and hence the cost is heightened.